Národní úložiště šedé literatury Nalezeno 2 záznamů.  Hledání trvalo 0.12 vteřin. 
AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (oponent) ; Fujcik, Lukáš (vedoucí práce)
This thesis deals with the designs of the functional verification model and the synthesizable tester of the 10Gb Ethernet devices that use XGMII interface. VHDL programming language is used to describe the model. This thesis consists of the creation of the bus functional model and the design of the tester that is implemented as a generic self-test module. The resulting design allows for verification and testing of the PHY and MAC layers. DE5-Net development board was used in the implementation of the tester. The board was fitted with FPGA Stratix V circuit, by Altera.
AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (oponent) ; Fujcik, Lukáš (vedoucí práce)
This thesis deals with the designs of the functional verification model and the synthesizable tester of the 10Gb Ethernet devices that use XGMII interface. VHDL programming language is used to describe the model. This thesis consists of the creation of the bus functional model and the design of the tester that is implemented as a generic self-test module. The resulting design allows for verification and testing of the PHY and MAC layers. DE5-Net development board was used in the implementation of the tester. The board was fitted with FPGA Stratix V circuit, by Altera.

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